1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device (EEPROM) which is electrically rewritable, and particularly, which multi-value-stores more information than 1-bit information in one memory cell.
2. Description of the Related Art
As one of EEPROMs, a NAND cell type EEPROM which can be integrated at a high density is known. In a NAND cell, a plurality of memory cells are coupled in series with each other such that a source and a drain are shared by adjacent memory cells. One terminal of the NAND cell is coupled to a bit line. Each memory cell generally has a structure obtained by stacking a floating gate (charge storage layer) and a control gate. A memory cell array is integrally formed in a p-type substrate (or a p-type well formed in an n-type substrate). The drain of the NAND cell is coupled to the bit line through one selective transistor, and the source of the NAND cell is coupled to a common source line through the other selective transistor. The control gates of the memory cells are coupled to word lines continuously arranged in a row direction.
The operation of the NAND cell type EEPROM is as follows.
Data are sequentially written in the memory cells from the memory cell located at the position farthest from the bit line. A data write operation is performed such that a high potential Vpp (=about 20 V) is applied to the control gate of a selected memory cell, an intermediate potential Vppm (=about 10 V) is applied the control gate and selective gate of a memory cell closer to the bit line than the selected memory cell, and 0 V or an intermediate potential Vm (=about 8 V) is applied to the bit line in accordance with data to be written in the memory cells.
More specifically, when 0 V is applied to the bit line, this potential is transferred to the drain of the selected memory cell, and electrons are injected from the drain to the charge storage layer. In this manner, the threshold voltage of the selected memory cell is shifted from an initial negative value in a positive direction. This state is represented by, e.g., `1`. When the intermediate potential Vm is applied to the bit line, electron injection does not effectively occur. For this reason, the threshold voltage does not change, and the threshold voltage is kept negative. This state is represented by `0`. The data write operation is simultaneously performed for memory cells which share a control gate.
A data erasing operation is simultaneously performed for all the memory cells in the NAND cell.
More specifically, all the control gates are set at 0 V, and a p-type well is set at 20 V. At this time, the selective gates, the bit line, and the source line are set at 20 V. Therefore, electrons of the charge storage layer are discharged into the p-type well, the threshold voltage is shifted in a negative direction, and the states of all the memory cells are set at `0`.
A data read operation is performed such that the control gate of a selected memory cell is set at 0 V, the control gates and selective gates of the remaining memory cells are set at a power supply potential Vcc (to be referred to as only Vcc hereinafter), and it is checked whether a current flows in the selected memory cell (state `0`) or not (state `1`).
Due to the limitation of the read operation, the threshold voltage after `1` has been written must be controlled to fall within a range of 0 V to Vcc. For this purpose, a write verify operation is performed, a memory cell set in an insufficient `1` write state is detected, and rewrite data is set such that a rewrite operation is performed for only the memory cell set in the insufficient `1` write state (bit-by-bit verify). The memory cell set in the insufficient `1` write state is detected by performing a read operation (verify read operation) while the selected control gate is set at, e.g., 0.5 V (verify potential).
In this case, the threshold voltage of the memory cell has a margin with respect to 0 V. For this reason, if the potential of the control gate is less than 0.5 V, a current flows in the selected memory cell, and the memory cell is detected as a memory cell set in an insufficient `1` write state. A current flows in a memory cell set in a `0` write state. For this reason, a circuit called a verify circuit for compensating for the current flowing in the memory cell is arranged to prevent the memory cell from being erroneously defined as a memory cell having the sufficient `1` write state. This verify circuit performs a write verify operation at a high speed.
As described above, when the data write operation is performed while the write operation and the write verify operation are repeated, a time for writing data in each memory cell is optimized, and the threshold voltage after `1` has been written is controlled to fall within a range of 0 V to Vcc.
In the NAND cell type EEPROM, a so-called multi-value storing cell in which states after the write operation are represented by n data, i.e., data `0`, `1`, `2`, . . . , and `n` is proposed. In a ternary storing cell (n=3), three states after the write operation are defined as follows. For example, a threshold voltage is negative in a `0` write state, a threshold voltage is 0 V to Vcc/2 in a `1` write state, and a threshold voltage is Vcc/2 to Vcc in a `2` write state.
FIG. 1 shows an arrangement of a ternary storing NAND cell type EEPROM proposed by the present inventors in corresponding U.S. application Ser. No. 08/308,534.
A ternary storing NAND cell type EEPROM has a bit line control circuit 2 for controlling the bit lines of memory cell arrays 1a and 1b in a read/write operation, and a word line driving circuit 6 for controlling the word line potentials of the memory cell arrays 1a and 1b.
The bit line control circuit 2 selects a predetermined bit line on the basis of a column decoder 3. The bit line control circuit 2 transmits and receives write/read data to/from an input/output data converting circuit 4 through a data input/output line (I/O line).
The input/output data converting circuit 4 converts the multi-value information read out from the memory cell into binary information to externally output the multi-value information, and converts the binary information of externally input write data into the multi-value information of the memory cell. The input/output data converting circuit 4 is coupled to a data input/output buffer 5 for controlling an input/output operation between the data input/output buffer 5 and an external circuit.
FIG. 2 shows the memory cell arrays 1a and 1b of the NAND cell type EEPROM in FIG. 1 and a related art's bit line control circuit 2. One terminal of a NAND cell is coupled to a bit line BLa, and the other terminal is coupled to a common source line Vsa. One terminal of another NAND cell is coupled to a bit line BLb, and the other terminal is coupled to a common source line Vsb. Selective gates SG1a, SG2a, SG1b, and SG2b and control gates CG1a to CG8a and CG1b to CG8b are shared by a plurality of NAND cells, and memory cells M which share one control gate constitute a page.
Each memory cell stores data on the basis of a threshold voltage Vt of the corresponding memory cell, and stores data `0`, `1`, and `2`. Since one memory cell has three states, nine combinations can be obtained by two memory cells. Eight combinations of the nine combinations are used to store 3-bit data in two memory cells. In this example, a pair of adjacent two memory cells which share a control gate store 3-bit data. The memory cell arrays 1a and 1b are formed on a dedicated p-type well.
A flip-flop FF1 constituted by n-channel MOS transistors Qn8 to Qn10 and p-channel MOS transistors Qp3 to Qp5 and a flip-flop FF2 constituted by n-channel MOS transistors Qn11 to Qn13 and p-channel MOS transistors Qp6 to Qp8 latch write/read data. The flip-flops FF1 and FF2 also operate as sense amplifiers. The flip-flop FF1 latches write data information indicating that "`0` is written or one of `1` and `2` is written`, and the flip-flop FF1 latches read data information indicating that the memory cell `holds information of `0` or holds one of information of `1` and information of `2`". The flip-flop FF2 latches write data information indicating that "`1` is written or `2` is written`". The flip-flop FF2 latches read data information indicating that a memory cell `holds information of `2` or holds one of information of `0` and information of `1`".
When a precharge signal .phi. pa goes `H`, an n-channel MOS transistor Qn1 transfers a potential Va to the bit line BLa. When a precharge signal .phi. pb goes `H`, an n-channel MOS transistor Qn20 transfers a potential Vb to the bit line BLb. N-channel MOS transistors Qn4 to Qn7 and p-channel MOS transistors Qp1 and Qp2 selectively transfer potentials VBHa, VBMa, and VBLa to the bit line BLa in accordance with the data latched in the flip-flops FF1 and FF2. N-channel MOS transistors Qn14 to Qn17 and p-channel MOS transistors Qp9 and Qp10 selectively transfer potentials VBHb, VBMb, and VBLb to the bit line BLb in accordance with the data latched in the flip-flops FF1 and FF2.
When a signal .phi. a1 goes `H`, an n-channel MOS transistor Qn2 couples the flip-flop FF1 to the bit line BLa. When a signal .phi. a2 goes `H`, an n-channel MOS transistor Qn3 couples the flip-flop FF2 to the bit line BLa. When a signal .phi. b1 goes `H`, an n-channel MOS transistor Qn19 couples the flip-flop FF1 to the bit line BLb. When a signal .phi. b2 goes `H`, an n-channel MOS transistor Qn18 couples the flip-flop FF2 to the bit line BLb.
The operation of the EEPROM arranged as described above will be described below with reference to FIGS. 3 to 5. FIG. 3 shows read operation timings, FIG. 4 shows write operation timings, and FIG. 5 shows verify read operation timings. In the following description, a case wherein a control gate CG2 is selected is exemplified.
A read operation will be described below with reference to FIG. 3. The read operation is performed in two basic cycles.
In the first read cycle, when the potential is set at 3 V, the bit line BLb serving as a reference bit line is precharged. When the precharge signal .phi. pa goes `L`, the selective bit line BLa floats, and the common source line Vsa is set at 6 V. The selective gates SG1a and SG2a and control gates CG1a and CG3a to CG8a are set at 6 V. At the same time, the selected control gate CG2a is set at 2 V. The bit line BLa is charged to a predetermined potential in accordance with the data of the selected memory cell.
When flip-flop activating signals .phi. n1 and .phi. p1 go `L` and `H`, respectively, the flip-flop FF1 is reset. When the signals .phi. a1 and .phi. b1 go `H`, the flip-flop FF1 is coupled to the bit lines BLa and BLb. When the signals .phi. n1 and .phi. p1 go `H` and `L`, respectively, the potential of the bit line BLa is sensed with reference to the potential of the reference bit line BLb, and the flip-flop FF1 latches information indicating `data `0` or one of data `1` and data `2`".
In the second read cycle, unlike in the first read cycle, the potential of the reference bit line BLb is not 3 V but 1 V, and signals .phi. a2, .phi. b2, .phi. n2, and .phi. p2 are output in place of the signals .phi. a1, .phi. b1, .phi. n1, and .phi. p1 to operate the flip-flop FF2. Therefore, in the second read cycle, information indicating `data `2` or one of data `1` or data `0`" is latched in the flip-flop FF2.
With the two read cycles, data written in the memory cell is read out.
Data in the memory cell is erased prior to a data write operation, and a threshold voltage Vt of the memory cell is -1.5 V or less. An erasing operation is performed such that the p-type well, the common source line Vsa, the selective gates SG1a and SG2a are set at 20 V, and the control gates CG1a to CG8a are set at 0 V.
A write operation will be described below with reference to FIG. 4.
Write data data1 and data2 are latched in the flip-flops FF1 and FF2, respectively. The data data1 is data for controlling "`0` write operation or one of `1` write operation and `2` write operation`". A node N1 is at `n` in the `0` write operation, and the node N1 is at `H` in one of the `1` write operation and the `2` write operation. The data data2 is data for controlling "`1` operation or `2` write operation`". A node N3 is at `L` in the `1` write operation, and the node N2 is at `H` in the `2` write operation.
When the precharge signal .phi. pa goes `L`, the bit line BLa floats. The selective gate SG1a is set at Vcc, and the control gates CG1a to CG8a are set at Vcc. The selective gate SG2a is at 0 V in the write operation. At the same time, a signal VRFYa goes `H`, and a signal PBa goes `L`. In the `0` write operation, since data set at `L` is latched in the node N1 of the flip-flop FF1, the bit line BLa is charged to Vcc with the potential VBHa. In one of the `1` write operation and the `2` write operation, the bit line BLa floats.
The selective gate SG1a and the control gates CG1a to CG8a are set at 10 V, the potential VBHa and a potential Vrw are set at 8 V, and a potential VBMa is set at 1 V. At this time, when the `0` write operation is to be performed, the bit line BLa is charged to 8 V. In the `1` write operation, data is latched such that the node N3 of the flip-flop FF2 is set at `L`. For this reason, 1 V is applied to the bit line BLa by the potential VBMa. In the `2` write operation, the bit line BLa is set at 0 V by the potential VBLa. Thereafter, the selected control gate CG2a is set at 20 V.
In one of the `1` write operation and the `2` write operation, electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BLa and the control gate CG2a, thereby increasing the threshold voltage of the memory cell. In the `1` write operation, an amount of charge to be injected into the charge storage layer of the memory cell must be smaller than that of the `2` write operation. For this reason, the bit line BLa is set at 1 V to moderate the potential difference between the bit line BLa and the control gate CG2a to 19 V. In the `0` write operation, electron injection is suppressed by a bit line potential (=8 V), and the threshold voltage of the memory cell does not change. Upon completion of the write operation, the selective gate SG1a and the control gates CG1a to CG8a are set at 0 V, and the potential (=8 V) of the bit line BLa at the `0` write operation is reset to 0 V. When this order is reversed, the state of the `2` write operation is temporarily set, and erroneous data is written in the `0` write operation.
After the write operation, the write state of the memory cell is checked, and a verify read operation is performed to perform an additional write operation for a memory cell set in an insufficient write state. The verify read operation will be described below with reference to FIG. 5.
The verify read operation is similar to the first read cycle except that the data of the flip-flop FF1 is reversed, the potential Vb is set at Vcc, signals VRFYa and VRFYb are output, and, at this time, the potentials VBLb and VBMb are set at 2.5 V and 0.5 V, respectively. The potential of the reference bit line BLb is determined by the potentials Vb, VBLb, and VBMb and the data of the flip-flops FF1 and FF2. The signals VRFYa and VRFYb are output before the signal .phi. n1 and .phi. p1 go `L` and `H` respectively, after the selective gates SG1a and SG2a and the control gates CG1a to CG8a are reset to 0 V. More specifically, the signals VRFYa and VRFYb are determined after the potential of the bit line BLa is determined by the threshold voltage of a memory cell and before the flip-flop FF1 is reset.
The data reverse operation of the flip-flop FF1 will be described below.
When the potential Vb is set at 2.5 V, the bit line BLb serving as a reference bit line is precharged. When the precharge signals .phi. pa and .phi. pb go `L`, the bit lines BLa and BLb float. Subsequently, when the signal PBa goes `L`, the bit line BLa is charged with 2.5 V or more only when the node N1 is at `L. Thereafter, when the flip-flop activating signals .phi. n1 and .phi. p1 go `L` and `H`, respectively, the flip-flop FF1 is reset. When the signals .phi. a1 and .phi. b1 go `H`, the flip-flop FF1 is coupled to the bit lines BLa and BLb. When the signals .phi. n1 and .phi. p1 go `H` and `L`, respectively, the bit line potential is sensed.
With the above operation, the data of the flip-flop FF1 is reversed. At this time, in the flip-flops FF1 and FF2, the node N1 is set at `H` in a `0` write operation after the data reverse operation is performed, the node N1 is set at `L` at one of a `2` write operation and a `1` write operation after the data reverse operation is performed, and the node N3 is set at `H` in the `1` write operation and set at `L` in the `2` write operation.
In the verify read operation after `0` has been written, the node N1 is at `H`, and the n-channel MOS transistor Qn5 is in an ON state. For this reason, the signal VRFYa goes `H` independently of the state of a memory cell, and the bit line BLa is set at `L` by the potentials VBLa and VBMa which are at 0 V. Therefore, the bit line BLa is sensed by the flip-flop FF1 such that the node N1 is set at `L`, and rewrite data `0` is latched.
In the verify read operation after `1` has been written, the nodes N2 and N4 are at `H`. For this reason, when the signal VRFYb goes `H`, the reference bit line BLb is set at 2.5 V. Therefore, when the memory cell does not reach a `1` write state, the bit line BLa is at 2.5 V or more, and the bit line BLa is sensed by the flip-flop FF1 such that the node N1 is set at `H`, and rewrite data `1` is latched. When the memory cell reaches the `1` write state, the bit line BLa is at 2.5 V or less, and the bit line BLa is sensed by the flip-flop FF1 such that the node N1 is set at `L`. Rewrite data `0` is latched, and a threshold voltage does not change in the rewrite operation.
In the verify read operation after `2` has been written, the nodes N2 and N3 are set at `H`. For this reason, when the signal VRFYb goes `H`, the reference bit line BLb is set at 0.5 V. Therefore, when the memory cell does not reach a `2` write state, the bit line BLa is at 0.5 V or more, and the bit line BLa is sensed by the flip-flop FF1 such that the node N1 is set at `H`. Rewrite data `2` is latched. When the memory cell reaches the `2` write state, the bit line BLa is at 0.5 V or less, and the bit line BLa is sensed by the flip-flop FF1 such that the node N1 is set at `L`. Rewrite data `0` is latched, and the threshold voltage does not change in the rewrite operation.
With this verify read operation, rewrite data is set as shown in Table 1 on the basis of write data and the write state of the memory cell.
TABLE 1 ______________________________________ WRITE DATA 00011222 DATA OF MEMORY CELL 01201012 REWRITE DATA 00010220 ______________________________________
As is apparent from Table 1, a `1` write operation is performed for only a memory cell which is to be set in a `1` write state but is set in an insufficient `1` write state, and a `2` write operation is performed for only a memory cell which is to be set in a `2` write state but is set in an insufficient `2` write state.
When the write operation and the verify read operation are repeated, a data write operation is performed for each memory cell such that a write time is optimized.
Table 2 shows the potentials of the portions of a memory cell array in an erasing operation, a write operation, a read operation, and a verify read operation.
TABLE 2 __________________________________________________________________________ WRITE ERASING OPERATION READ VERIFY READ OPERATION "0" "1" "2" OPERATION OPERATION __________________________________________________________________________ BL 20 V 8 V 1 V 0 V SEE FIG. 5 SG1 20 V 10 V 6 V 6 V CG1 20 V 10 V 6 V 6 V CG2 0 V 20 V 2 V 2 V CG3 0 V 10 V 6 V 6 V CG4 0 V 10 V 6 V 6 V CG5 0 V 10 V 6 V 6 V CG6 0 V 10 V 6 V 6 V CG7 0 V 10 V 6 V 6 V CG8 0 V 10 V 6 V 6 V SG2 20 V 0 V 6 V 6 V VS 20 V 0 V 6 V 6 V p-well 20 V 0 V 0 V 0 V __________________________________________________________________________
As described above, when the bit line control circuit shown in FIG. 2 is used, a data write operation, a data verify read operation, a data read operation, and a data erasing operation can be performed for the memory cells of a ternary storing EEPROM.
However, the read operation requires two basic cycles, i.e., a first read cycle for determining "`0` or one of `1` and `2`" and a second read cycle for determining "`2` or one of `1` and `0`". The verify read operation also requires two basic cycles, i.e., a reverse cycle and a verify cycle. Therefore, each operation requires a long time.
As described above, in the ternary (multi-value) EEPROM having the bit line control circuit shown in FIG. 2, the read operation requires the two basic cycles, i.e., the first read cycle and the second read cycle, and the verify read operation requires the two basic cycles, i.e., the reverse cycle and the verify cycle. Therefore, each operation requires a long time.